1. Field of the Invention
The present invention relates to a memory device, and more particularly, to a reference level generator in a memory device.
2. Background of the Related Art
A ferroelectric memory, i.e., an FRAM (Ferroelectric Random Access Memory), has in general a data processing speed similar to a DRAM dynamic Random Access Memory) which is used widely as a semiconductor memory. Because the FRAM can conserve data even if the power is turned off, much attention has been given to FRAM as a next generation memory. The FRAM, a memory having a structure similar to the DRAM, is provided with a capacitor of a ferroelectric material for utilizing a high residual polarization of the ferroelectric material. The residual polarization permits the conservation of a data even after removal of an electric field.
FIG. 1 illustrates a characteristic curve of a hysteresis loop of a general ferroelectric material. A polarization induced by an electric field is not erased, but a certain amount (xe2x80x98dxe2x80x99 and xe2x80x98axe2x80x99 states) remains, even if the electric field is removed owing to existence of the residual polarization (or spontaneous polarization). The xe2x80x98dxe2x80x99 and xe2x80x98axe2x80x99 states correspond to xe2x80x981xe2x80x99 and xe2x80x980xe2x80x99, respectively, in application to memories.
FIG. 2 illustrates a system of unit cell of the related art non-volatile ferroelectric memory. The system of a unit cell of the related art non-volatile ferroelectric memory is provided with a bitline BL formed in one direction, a wordline W/L formed in a direction perpendicular to the bitline, a plateline P/L formed spaced from the wordline in a direction identical to the wordline, a transistor T1 having a gate connected to the wordline W/L and a source connected to the bitline BL, and a ferroelectric capacitor FC1 having a first terminal connected to a drain of the transistor T1 and a second terminal connected to the plateline P/L.
FIG. 3A illustrates a timing diagram of a write mode operation of the related art ferroelectric memory. In a writing mode, when an external chip enable signal CSBpad changes from xe2x80x98highxe2x80x99 to xe2x80x98lowxe2x80x99 and a write enable signal WEBpad changes from xe2x80x98highxe2x80x99 to xe2x80x98lowxe2x80x99 simultaneously, the write mode is enabled or initiated. When an address decoding is started in the write mode, a pulse applied to a relevant wordline is transited from xe2x80x98lowxe2x80x99 to xe2x80x98highxe2x80x99 to select a cell. Thus, during a period the wordline is held xe2x80x98highxe2x80x99, a relevant plateline has a xe2x80x98highxe2x80x99 signal applied thereto for one period and a xe2x80x98lowxe2x80x99 signal applied thereto for the other period in succession.
In order to write a logical value xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99 on the selected cell, a xe2x80x98highxe2x80x99 or xe2x80x98lowxe2x80x99 signal synchronized to the write enable signal WEBpad is applied to a relevant bitline. If a xe2x80x98highxe2x80x99 signal is applied to the bitline and a signal applied to the plateline is xe2x80x98lowxe2x80x99 in a period in which a signal applied to the wordline is xe2x80x98highxe2x80x99, a logical value xe2x80x981xe2x80x99 is written on the ferroelectric capacitor. If a xe2x80x98lowxe2x80x99 signal is applied to the bitline and a signal applied to the plateline is xe2x80x98highxe2x80x99, a logical value xe2x80x980xe2x80x99 is written on the ferroelectric capacitor.
The operation for reading the data stored in the cell by the aforementioned write mode operation will be explained.
FIG. 3B illustrates a timing diagram of a read mode operation of the related art ferroelectric memory. If the chip enable signal CSBpad changes from xe2x80x98highxe2x80x99 to xe2x80x98lowxe2x80x99 from outside of the chip, all bitlines are equalized to a xe2x80x98lowxe2x80x99 voltage before a relevant wordline is selected. After the bitlines are disabled, an address is decoded, and the decoded address causes a xe2x80x98lowxe2x80x99 signal on a relevant wordline to transit to a xe2x80x98highxe2x80x99 signal, to select a relevant cell. A xe2x80x98high.xe2x80x99 signal is applied to the plateline of the selected cell, to break a data corresponding to a logical value xe2x80x981xe2x80x99 stored in the ferroelectric memory. If a logical value xe2x80x980xe2x80x99 is in storage in the ferroelectric memory, a data corresponding to the logical value xe2x80x980xe2x80x99 is not broken. As the data not broken and the data broken provide values different from each other according to the aforementioned hysteresis loop, the sense amplifier can sense a logical value xe2x80x981xe2x80x99 or xe2x80x980xe2x80x99.
The case of the data broken is a case when the value is changed from xe2x80x98dxe2x80x99 to xe2x80x98fxe2x80x99 in the hysteresis loop of FIG. 1, and the case of the data not broken is a case when the value is changed from xe2x80x98axe2x80x99 to xe2x80x98fxe2x80x99 in the hysteresis loop of FIG. 1. Therefore, if the sense amplifier is enabled after a certain time period has passed, in the case of the data broken, a logical value xe2x80x981xe2x80x99 is provided as amplified, and in the case of the data not broken, a logical value xe2x80x980xe2x80x99 is provided. After the sense amplifier provides the data and since an original data should be restored, the plateline is disabled from xe2x80x98highxe2x80x99 to xe2x80x98lowxe2x80x99 in a state a xe2x80x98highxe2x80x99 signal is applied to a relevant wordline.
FIG. 4 illustrates a block diagram of a related art nonvolatile ferroelectric memory. The related art nonvolatile ferroelectric memory is provided with a main cell array 41 having a lower portion allocated for a reference cell array 42, a wordline driver 43 on one side of the main cell array 41 for providing a driving signal to the main cell array 41 and the reference cell array 42, and a sense amplifier unit 44 formed under the main cell array 41. The wordline driver 43 provides a driving signal to the main wordline for the main cell array 41 and the reference wordline for the reference cell array 42. The sense amplifier unit 44 has a plurality of sense amplifiers each for amplifying bitlines and bitbarlines.
The operation of the aforementioned nonvolatile ferroelectric memory will be explained with reference to FIG. 5, which illustrates a partial detail of FIG. 4, wherein the main cell array has a folded bitline structure. The reference cell array 42 also has a folded bitline structure, and two pairs of a reference cell wordline and a reference cell plateline are provided, which are defined as RWL_1, RPL_1 and RWL_2, RPL_2 . . . RWL_Nxe2x88x921, PRL_Nxe2x88x921, and RWL_N, RPL_N, respectively.
Provided that the main cell wordline MWL_Nxe2x88x921 and the main cell plateline MPL_Nxe2x88x921 is enabled, the reference cell wordline RWL_Nxe2x88x921 and the reference cell plateline RPL_Nxe2x88x921 are enabled. Therefore, a data from the main cell is loaded on the bitline BL, and a data from the reference cell is loaded on the bitbarline /BL. When the main cell wordline MWL_N and the main cell plateline MPL N are enabled, the reference cell wordline RWL_N and the reference cell plateline RPL_N are also enabled. Therefore, a data from the main cell is loaded on the bitbarline /BL, and a data from the reference cell is loaded on the bitline BL. In this instance, a bitline level REF caused by the reference cell is between bitline levels B_H(High) and B_L (Low) caused by the main cell.
In order to position the reference voltage REF between the bitline levels B_H and B_L, two reference cell operation methods can be used. The first method stores logic xe2x80x9c1xe2x80x9d in the capacitor of the reference cell, which can be achieved by providing a capacitor of a reference cell of which size is smaller than a capacitor size of the main cell. The second method stores a logic xe2x80x9c0xe2x80x9d in the capacitor of the reference cell, which can achieved by providing a capacitor of a reference cell of which size is larger than a capacitor size of the main cell. Thus, the related art nonvolatile ferroelectric memory can produce a reference voltage required by the sense amplifier unit 44 by using the foregoing two methods.
However, the aforementioned related art nonvolatile ferroelectric memory has various problems. For example, when a capacitor size of the reference cell is made smaller than a capacitor size of the main cell as the first method for providing a level of the reference voltage to be between the bitline levels B_H and B_L, when the reference cell capacitor is excessively switched, i.e., destructed, in comparison to the main cell, the reference cell experiences fatigue before the main cell, which can lead to an unstable reference voltage. Further, when a capacitor size of the reference cell is made larger than a capacitor size of the main cell as the second method for providing a level of the reference voltage to be between the bitline levels B_H and B_L, although fatigue may not be a problem, the capacitor size increases, leading to an increase in size of the FRAM.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
An object of the present invention is to provide a stable reference voltage.
Another object of the present invention is tor provide an improved data sensing reliability.
An object of the present invention and other advantages can be achieved in a whole or in parts by a reference level generating circuit for a memory device comprising: a first amplifier and a second amplifier, each for comparing and amplifying a reference bitline level and a fedback preliminary reference level; a reference level adjuster for receiving signals from the first and second amplifiers, adjusting the signals to desired reference levels, and feeding the signals back to the first and second amplifiers; and a reference level stabilizer for stabilizing a reference level from the reference level adjuster.
An object of the present invention and other advantages can be achieved in a whole or in parts by a reference level generating circuit in a nonvolatile ferroelectric memory includes a first amplifier and a second amplifier each for comparing and amplifying a reference bitline level and a fedback preliminary reference level, a reference level adjuster for receiving signals from the first and second amplifiers, adjusting the signals to desired reference levels, and feeding the signals back to the first and second amplifiers, a reference level stabilizer for stabilizing a reference level from the reference level adjuster, a pull-down circuit for dropping an output from the reference level stabilizer by a required level in bitline precharging, and an operation controller for controlling operation of the first and second amplifiers, the reference level adjuster, the reference level stabilizer, and the pull-down circuit.
An object of the present invention and other advantages can be achieved in a whole or in parts by a reference level generating circuit in a nonvolatile ferroelectric memory comprising: an operation controller including a first PMOS transistor for switching a power source voltage in response to a first control signal; a first amplifier including a second PMOS transistor having a source connected to an output terminal on the first PMOS transistor, and a gate and a drain connected in common, a third PMOS transistor connected in parallel with the second PMOS transistor with respect to an output terminal on the first PMOS transistor, a first NMOS transistor having a gate connected to a reference bitline and a source connected to the second PMOS transistor, a second NMOS transistor formed between a drain of the first NMOS transistor and a grounding terminal and controlled by a drain voltage of the second PMOS transistor, and a third NMOS transistor connected between the third PMOS transistor and the second NMOS transistor, for comparing and amplifying a signal from the reference bitline and a fedback signal; a second amplifier including a fourth PMOS transistor having a source connected to the output terminal on the operation controller, a fifth PMOS transistor connected in parallel with the fourth PMOS transistor with respect to the output terminal on the operation controller, a fourth NMOS transistor having a gate connected to the reference bitline and a source connected to a drain of the third PMOS transistor, a fifth NMOS transistor formed between a drain of the fourth NMOS transistor and a grounding terminal, and a sixth NMOS transistor formed between the fifth PMOS transistor and a drain of the fifth NMOS transistor, for comparing and amplifying a signal from the reference bitline and a fedback signal; a reference level adjuster including a seventh NMOS transistor formed between the output terminal on the operation controller and a gate of the third NMOS transistor and controlled by a drain voltage of the third PMOS transistor, an eighth NMOS transistor formed between a drain of the third PMOS transistor and a drain of the seventh NMOS transistor and controlled by a source voltage of the fourth NMOS transistor, a sixth PMOS transistor having a source connected to the output terminal on the operation controller and controlled by the first control signal, and a seventh PMOS transistor formed between the sixth PMOS transistor and a gate of the third NMOS transistor and controlled by a source voltage of the fourth NMOS transistor, for receiving a signal from the first and second amplifiers and adjusting to a desired level; a reference level stabilizer including a ninth NMOS transistor having a source connected to an output terminal on the reference level adjuster and controlled by a source voltage of the fourth NMOS transistor, a tenth NMOS transistor connected to the ninth NMOS transistor in series and controlled by a source voltage of the sixth NMOS transistor, and an eleventh NMOS transistor having a source connected to an output terminal on the reference level adjuster and a drain connected to a drain of the tenth NMOS transistor and controlled by an external second control signal, for stabilizing a reference level from the reference level adjuster; and a pull-down circuit including a twelfth NMOS transistor connected in parallel with a drain of the tenth NMOS transistor and controlled by the first control signal, and a thirteenth NMOS transistor formed between a drain of the twelfth NMOS transistor and a grounding terminal and having a gate and a drain connected in common, for dropping a reference level from the reference level stabilizer down to a threshold voltage level of an NMOS transistor in precharging the bitline.
An object of the present invention and other advantages can be achieved in a whole or in parts by a memory device comprising: a memory cell array having a main cell array of plurality of main memory cells and a reference cell array of a plurality of reference memory cells; a wordline driver that provides driving signals to select a corresponding number of main memory cells and reference memory cells; and a sense amplifier unit used for reading data from and writing data to the memory cell array, wherein the reference cell array is formed between the wordline driver and the main cell array.
An object of the present invention and other advantages can be achieved in a whole or in parts by a method of generating a reference voltage comprising: comparing and amplifying a reference bitline level and a feedback preliminary reference level in response to a switched voltage; adjusting the amplified bitline level and the feedback preliminary reference level; and stabilizing the feedback preliminary reference level.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.